1. Field of the Invention
A first method described here is for discretionary fine-grain resist layer patterning in situ to a fixed mask pattern exposure for fabrication of integrated circuits, and a second method described here requires the fabrication of a custom mask to pattern on each wafer a discretionary layer incorporating all discretionary changes for a specific lot of wafers.
2. Description of the Prior Art and Related Prior Patents
Integrated circuits (ICs) include active and passive elements such as transistors, diodes, resistors, and capacitors, that are interconnected in a predetermined pattern to perform desired functions. The interconnections are effectuated by means of metallization layers and vias. A "via" is a hole through an insulation layer in which conductor material is located to electrically interconnect one conductive layer to another or to an active or passive region in the underlying semiconductor substrate. Present day technology generally employs two metallization layers that are superimposed over the semiconductor wafer structure. Integrated circuits and assemblies have become more complex with time and in a logic circuit, the number of integrated circuit logic units (ICLUs) and interconnects on a given size die have been substantially increased reflecting improved semiconductor processing technology. An ICLU is an IC element and can be a device (such as a transistor), a gate (several transistors) or as many as 25 or more transistors and other devices. As is well known in the art, each ICLU is connected to other ICLUs by conductive contact points which have a typical center-to-center spacing of about 6 to 15 microns (.mu.m).
Standard processing to make logic structures (e.g., gate arrays) includes first fabricating as many as half a million transistors comprising a quarter of a million gates per die. Each semiconductor wafer (typically silicon but sometimes of other material such as gallium arsenide) includes many die, for example, several hundred. In one type of gate array, for example, the transistors are arrayed in rows and columns on each die, and each transistor is provided with conductive contact points (typically metal but sometimes formed of other conductive material such as doped polycrystalline silicon), also arrayed in rows and columns.
In the prior art, the next step is to use fixed masks to fabricate the conductive layers (sometimes called "metallization layers"), to connect together the individual gate-array devices. Typically two or sometimes three metallization layers are used.
After this, the completed die is tested. If any of the devices on the die are defective, that die will fail an exhaustive test and be scrapped. Therefore, the more transistors per die the lower the manufacturing yield. In some cases redundant sections of a circuit are provided that can be substituted for defective sections of a circuit by fuses after metallization. Typically such redundant sections can be 5% to 10% of the total circuit.
As stated above, the prior art fabricates a plurality of transistors on a die, interconnects the transistors to form desired logic, tests the entire die, and scraps the die if the logic doesn't work. In the contrasting methods as disclosed in the related patents listed above, after fabricating the transistors exactly as before, the transistors or ICLUs are tested individually (see related patents listed above for details.). Then the interconnect scheme is modified, if necessary, by CAD means (of well known design) to bypass defective transistors or ICLUs and substitute, logically speaking, replacement (redundant) ICLUs. Then the metallization layers are deposited and patterned in accordance with the modified interconnect scheme, in one embodiment by E-beam (Electron-beam) lithography, instead of the masking process of the usual conventional technology. Thus each die has its own unique interconnect scheme, even though each die is to carry out the same function as the other die.
One begins with a gate array IC conventionally fabricated on a silicon or GaAs wafer although standard cell or full custom IC designs can just as easily be used. The gate array transistors are arrayed in columns and rows on the wafer surface 1 of FIG. 1a, and the active regions of each transistor are provided with contact points such as 2-1 to 2-32 which are in columns and rows as shown in FIG. 1b (not all contact points are numbered). FIG. 1b is an enlarged view of the portion of FIG. 1a shown in the circle marked "1b". Redundant (or extra) devices are designed into each column, with a redundancy factor dependent on the expected yield of the individual transistors or ICLUs being tested.
The surface of the wafer 1 is optionally planarized with a cured layer of polyimide 0.8 to 1.5 micron thick if the step heights between contact points are greater than 0.5 microns. (The contact points 2-1 to 2-32 are masked from the polyimide layer, to create a via over each contact point free of polyimide, and metal is deposited to fill the via.)
The fabricated (but not metallized) wafer 1 is now ready for testing. Sometimes only one column of transistors on each die is tested at a time; testing more than one column, the whole die or several die per step is also possible. For a die of typical complexity this requires making contact with all of the perhaps 10,000 or so contact points such as 2-1 to 2-4 in one column simultaneously, and then stepping across all 100 or 200 or more columns in each die, to exhaustively test each die in step-and-repeat fashion. Each contact point such as 2-1 is small such as usually 4.times.4 microns in area. Each wafer contains a plurality of die, the exact number depending on the size of the wafer but typically being in the hundreds.
The data resulting from the testing is a list of the location of each of the defective transistors or ICLUs. This list is automatically communicated to a conventional CAD system from a tester signal processor. The CAD system then, by special software algorithms, works out interconnect changes for each die. Each interconnect change required due to a defective ICLU typically affects ICLU interconnects over an area of no greater than 100 .mu.m in diameter. Therefore, the master placement scheme of the net list is modified in terms of the placement of the defective ICLUs so as to bypass the defective ICLUs and interconnect defect-free ICLUs from the stock of redundant ICLUs.
The above-mentioned related patents listed above (as described in detail therein) use two alternative software algorithms for interconnects: recomputation of metallization trace routing or a CAD rip-up router.
A modified routing database as provided by either of these methods is next used to produce the database for the desired interconnect patterns on the wafer using in one embodiment E-beam equipment. The metallization process is in one embodiment a two layer metallization, although a single layer of metallization or three or more layers of metallization can also be used. The metallization process involves depositing a layer of insulation, such as silicon dioxide, typically of about one micron thickness over the wafer surface, and cutting vias by means of a mask to the contact points on the wafer surface through the silicon dioxide layer. Then a layer of metal, typically aluminum, is deposited over the silicon dioxide. Then a layer of photoresist is deposited and patterned, for example using E-beam (maskless) lithography. The E-beam is controlled by the CAD database means and its modified net list to make the desired interconnect pattern corrected in accordance with the test results. The photoresist is then developed and removed where exposed to the E-beam (if positive resist), allowing the patterning of the interconnects as desired.
The metallization (i.e., interconnect) process is then repeated for the second metallization layer and any subsequent metallization layers. The metallization process is generally well known technology.
At this point the wafer is complete, ready for scribing, packaging and final test as usual.